FIG. 12 is a schematic view showing a conventional layout pattern of an end portion of a memory array. As shown in FIG. 12, in a conventional semiconductor memory device, in order to prevent a density difference of a mask pattern (further a characteristic variation due to the density difference) from being generated as far as possible between element blocks A (a group of transistors forming memory cells, sense amplifiers and so on) which are arranged in an end portion of the memory array (a portion adjacent to a peripheral perimeter of the memory array) and element blocks B (a group of transistors forming memory cells, sense amplifiers and so on, like the element blocks A) which are not arranged in the end portion of the memory array, dummy blocks D1 and D2 which are not in practical use are provided adjacent to the element blocks A.
However, the conventional semiconductor memory device has a problem of unnecessary increase in an area of the memory array since each of the dummy blocks D1 and D2 has the same size as the element block A. In particular, as shown in FIG. 13, if a plurality of divided memory arrays is arranged, this problem becomes more remarkable since an area of the dummy blocks D1 and D2 increases with an increase in the area of end portions of the memory arrays.